"Avoid using set_max_delay on a path that already has a clock. This overrides the default setup relationship and usually results in over-optimization, increasing area by 20%."
: Use set_false_path for paths that shouldn't be timed and set_multicycle_path for data paths allowed more than one clock cycle to complete. Management and Verification synopsys timing constraints and optimization user guide 2021
For more information on Synopsys' timing constraints and optimization capabilities, refer to the following resources: "Avoid using set_max_delay on a path that already
For the physical synthesis flow (IC Compiler), the guide discusses: The 2021 guide reinforces a golden rule of
Specifying when data arrives at a port relative to a clock edge.
The 2021 guide reinforces a golden rule of digital design: a design is only as good as its constraints. The documentation spends significant time refining the usage of create_clock and create_generated_clock , emphasizing that over-constraining or under-constraining are equally fatal to design integrity.
: When the standard single-cycle timing model is too restrictive, exceptions are used: